The present invention relates to a data reading method and a data writing method in a semiconductor memory device such as a ferroelectric memory, for example, and a semiconductor memory device for carrying out the data reading method or the data writing method.    [Patent Literature 1] U.S. Pat. No. 4,873,664    [Patent Literature 2] Japanese Patent Laid-Open No. 2002-197857    [Patent Literature 3] Japanese Patent Laid-Open No. Hei 9-116107
Various semiconductor memories using new memory materials have recently been proposed. Many of these memories are nonvolatile but capable of high speed operation equal to a DRAM, and thus promise to be applied in the future as “next-generation memories.” A typical example of such memories is a ferroelectric memory. A cell structure and operation of a currently mainstream ferroelectric memory are disclosed in Patent Literature 1.
FIG. 16 represents an example of a method of realizing the ferroelectric memory.
In a structure shown in FIG. 16, a memory cell is formed by one access transistor Ta and one ferroelectric capacitor C. The memory cell stores two values, that is, 1 bit according to a direction of polarization of the ferroelectric capacitor C.
A word line decoder/driver 1 applies a voltage to word lines WL (WL1, WL2 . . . ) according to an address to be accessed. A predetermined word line WL applies a voltage to a gate electrode of the access transistor Ta in each memory cell. Therefore the memory cell is selected by driving the word line WL.
Bit lines BL (BL1, BL2 . . . ) are arranged in a direction orthogonal to the word lines WL.
The bit lines BL1 and BL2 form a bit line pair whose potential is detected by a sense amplifier 3-1. The bit lines BL3 and BL4 form a bit line pair whose potential is detected by a sense amplifier 3-2.
In each memory cell, the access transistor Ta is turned on by the word line WL, whereby the memory cell is connected to the corresponding bit line BL.
A plate line decoder/driver 2 applies a predetermined voltage to plate lines PL (PL1, PL2 . . . ).
A predetermined plate line PL is connected with one terminal of the capacitor C of each memory cell.
A data reading operation will be described with reference to a hysteresis curve of FIG. 17 by taking as an example data reading from a memory cell formed by a capacitor C(*) and an access transistor Ta(*) provided with (*) in FIG. 16 in such a configuration.
In reading data from the capacitor C(*), the word line WL3 is selected, and a pulse is applied to the plate line PL2. Then, since the access transistor Ta(*) of the memory cell is turned on, a signal read from the ferroelectric capacitor C(*) appears in the bit line BL1 connected to an opposite electrode of the ferroelectric capacitor C(*).
This state will be described with reference to FIG. 17. An axis of abscissas indicates voltage applied to the ferroelectric capacitor, and an axis of ordinates indicates amount of polarization.
In an initial state of reading, the plate line PL2 and the bit line BL1 are equalized to 0V, and the bit line BL1 is in a floating state.
The ferroelectric capacitor C(*) is polarized in a different direction according to data stored therein. For example, the capacitor with data of “0” is in an (H0) state, and the capacitor with data of “1” is in an (H1) state in FIG. 17.
A pulse of a voltage Vcc is applied to the plate line PL2, whereby substantially Vcc is applied to the capacitor C(*). Then, the amount of polarization is shifted to an (H2) state in both of the above cases. Accordingly a signal difference corresponding to a difference in amount of polarization change from the initial state appears as a signal difference in reading of “0” and “1” in the bit line BL1.
That is, only in a case where “1” data is stored in the “H1” state, the ferroelectric capacitor C(*) effects polarization inversion, and a signal difference corresponding to the inversion appears in the bit line BL1. Specifically, a potential of the bit line BL1 at the time of reading of the “1” data involving the polarization inversion is higher than that at the time of reading of the “0” data not involving the polarization inversion.
By for example supplying an intermediate potential between a read signal when the “1” data is stored and a read signal when the “0” data is stored as a reference signal to the bit line BL2 forming a pair, and comparing a read signal with the reference signal by the differential type sense amplifier 3-1, it is possible to determine whether the read signal is “1” or “0.”
The polarization inversion of such a ferroelectric capacitor can be performed at a high speed in about one nanosecond. Therefore the ferroelectric memory, though nonvolatile, can achieve as high an access speed as DRAM.
Incidentally, while a so-called folded bit line structure has been described in the above example, an open bit line structure or a structure for supplying a reference voltage directly to a sense amplifier without using a pair of bit lines is known as another structure. Principles of the operation and data determination are the same in these cases.
Patent Literatures 2 and 3 propose a cross point type ferroelectric memory as means for improving a degree of integration of the above-described ferroelectric memory.
FIG. 18 shows a circuit example of cross point type memory cells.
As shown in FIG. 18, cell strings SS (SS1, SS2 . . . ) include a plurality of (n) capacitors C1 to Cn connected to common node electrodes NE (NE1, NE2 . . . ).
The cell strings are connected to bit lines BL (BL1, BL2 . . . ) via access transistors Ta (Ta1, Ta2 . . . ) formed by a FET which transistors are controlled by word lines WL (WL1 . . .).
The capacitors C including the cell strings SS each store separate data, and are controlled by respective plate lines PL1 to PLn independent of each other.
In this circuit example, a potential of the bit line BL1 is detected by a sense amplifier 3-1, and a potential of the bit line BL2 is detected by a sense amplifier 3-2.
Data reading from the capacitor C1 of the cell string SS1 will be taken as an example.
In this case, when the word line WL1 is selected and a pulse is applied to the plate line PL1 with the plate lines PL2 to PLn fixed to 0 V, a different signal occurs in the bit line BL1 according to a direction of polarization of the ferroelectric capacitor C1 on the same principles as described above. The sense amplifier 3-1 compares the signal thus generated in the bit line BL1 with a reference signal supplied separately, and thereby determines whether the read signal is “1” or “0.”
This cross point type cell structure, in which one access transistor Ta is shared by the plurality of capacitors C1 to Cn, effectively reduces a number of elements per bit, and is thus effective in reducing cost.
Incidentally, it is needless to say that the cross point type has many structural variations such as a folded bit line structure, an open bit line structure and the like.
Patent Literature 2 further proposes a memory structure as a development of the cross point type, provided with a mechanism for amplifying a read signal. FIG. 19 shows an example of the memory structure.
A cell string SS includes a plurality of (n) ferroelectric capacitors C1 to Cn connected to a common node electrode NE. The capacitors C1 to Cn each store separate data, and are controlled by respective plate lines PL1 to PLn independent of each other.
Further, a reading access transistor Tr, a writing access transistor Tw, and a sense transistor Ts each formed by a FET are provided.
The sense transistor Ts is a depletion type N-channel MOS-FET. The sense transistor Ts has a gate connected to the common node electrode NE. One of a source and a drain of the sense transistor Ts is connected to a ground potential, for example, and the other is connected to a bit line BL via the reading access transistor Tr.
One of a source and a drain of the reading access transistor Tr is connected to the sense transistor Ts, and the other is connected to the bit line BL. A gate of the reading access transistor Tr is connected to a reading word line WLr, so that on/off control of the reading access transistor Tr is effected by the reading word line WLr.
One of a source and a drain of the writing access transistor Tw is connected to the common node electrode NE, and the other is connected to the bit line BL. A gate of the writing access transistor Tw is connected to a writing word line WLw, so that on/off control of the writing access transistor Tw is effected by the writing word line WLw.
Data reading from the capacitor C1 will be taken as an example. In this case, the reading word line WLr is selected and a pulse is applied to the plate line PL1 with the plate lines PL2 to PLn fixed to 0 V.
Thereby a signal appears at the common node electrode NE according to a direction of polarization of the ferroelectric capacitor C1. At this time, the writing word line WLw is turned off (the writing access transistor Tw is off), and hence the common node electrode NE is disconnected from the bit line BL.
That is, a charge from the cell capacitor C1 drives only the gate electrode of the sense transistor Ts rather than directly driving the bit line BL. The sense transistor Ts, which is for example a depletion type NMOS transistor, drives the bit line BL according to a voltage applied to the gate of the sense transistor Ts. Thus, in this case, an amplified signal obtained by converting the signal appearing at the common node electrode NE appears in the bit line BL.
At the time of data writing, on the other hand, the writing word line WLw is selected, and thus the writing access transistor Tw is turned on. The reading access transistor Tr is turned off. Then, the common node electrode NE is connected to the bit line BL. By driving the bit line BL and a plate line PL to respective required states, an appropriate voltage as a potential difference between the bit line BL and the plate line PL(x) is applied to a selected capacitor C(x), so that data is written to the selected capacitor C(x).
Such an amplification type memory can effectively extract a signal from a minute ferroelectric capacitor because of its signal amplification effect, and is thus very advantageous for a higher degree of integration. Further, such an amplification type memory does not increase cell area because the sense transistor Ts and the like as an added circuit for amplification can be formed in an empty silicon region under the cell string SS.
As described above, the ferroelectric memory, though nonvolatile, can realize high-speed rewriting operation, and has a potential for realizing a capacity higher than that of DRAM. The cross point type having the signal amplifying function as shown in FIG. 19, in particular, is advantageous for miniaturization because the cross point type amplifies even a signal of a minute capacitor into a large signal.
However, as the ferroelectric capacitor is made smaller, an error rate is increased due to signal variations.
Ferroelectric film does not have small variations in crystal orientation and amount of polarization because of imperfectness of its crystal. Such variations are averaged in large capacitors and thus do not present much of a problem, but become noticeable as the capacitors are made smaller. For example, when capacitor area and load capacitance are both reduced to ¼, an average signal value is directly scaled and unchanged, while statistical variations are increased twofold.
This problem cannot be solved merely by amplifying signals because the variations are also amplified.
Incidentally, such variations depend greatly on variations of ferroelectric components, and are generally noticeable particularly on a high level side (corresponding to “1” data in this case).
Effects of such signal variations on data determination are illustrated in a conceptual diagram of FIG. 20A. In the figure, signal levels “0” and “1” of memory cells shown by cell signals CS1, CS2, and CS3 are both varied, as indicated by ● and ◯. In addition, these signals are changed in a direction in which the “0” data and the “1” data approach each other, as indicated by x and Δ, due to data retention deterioration, disturb deterioration, and the like. For example, the cell signal CS1 changes with time from a state (α) to a state (β). That is, the “0” signal is raised in level, and the “1” signal is lowered in level, thus reducing a signal difference.
In determining data stored in memory cells, one reference signal corresponding to an intermediate level between “0” and “1” is used for the determination for the plurality of capacitors. A method is proposed in which for example one dummy capacitor for generating a reference potential is provided on a bit line and the determination for all memory cells on adjacent bit lines is made using the dummy capacitor.
Looking at a reference signal rf in FIG. 20A, however, the reference signal rf has a level appropriate for determining the cell signal CS1, for example, but causes an error with the cell signal CS2. An operating margin is further deteriorated with degradations with time of the signals as described above.
In order to solve such a problem, a method referred to as self-reference is proposed which makes an accessed capacitor itself generate a reference signal. This method is carried out by the following procedure.
1. After a first signal from initial data is obtained in a first reading, data corresponding to a low-level signal is temporarily written to the cell.
2. A second signal is obtained by performing a second reading.
3. The initial data is determined by comparing the first signal with a reference signal obtained by adding a fixed offset signal to the second signal.
In such a determination method, as shown in FIG. 20B, signals obtained by adding a fixed offset OF to a low level signal (corresponding to “0” data in this case) of each memory cell are provided as reference signals rf1, rf2, and rf3. Therefore variations on the “0” side are cancelled at all times.
However, variations on the “1” side, which are most problematic, are not cancelled. In addition, since a value of the offset OF is fixed for all cells, it is not possible to provide an optimum signal for each memory cell.
Thus, as shown in FIG. 20B, for example, even when the reference signal rf1 is appropriate for the cell signal CS1, the reference signal rf2 for the cell signal CS2 is too close to “1,” while the reference signal rf3 for the cell signal CS3 has a level shifted to the “0” side.
Since a sense amplifier makes read data determination by sensing a difference between each cell signal and a reference signal, when there is an imbalance as described above, the sense amplifier cannot obtain a sufficient difference in a particular state of a particular cell, thus decreasing determination sensitivity.
Further, in the case of data retention degradation with time or the like, a “0” signal written as a reference is fresh, and is thus smaller than a retained “0” signal. Therefore too small an offset causes an error in reading of “0,” and too large an offset causes an error in reading of “1.” Thus setting of an appropriate value of the offset OF itself is very difficult.
The ferroelectric memory also has the following problem in writing operation.
Currently, the polarization inversion of the ferroelectric memory requires application of a voltage of 1.5 to 3 V. Lowering this value requires thinning ferroelectric film; however, this cannot be readily carried out because of problems of capacitor leakage and withstand voltage. On the other hand, with reduction in size of transistors, operating voltage of a logic circuit within a chip has continued to decrease, thus resulting in a mismatch between operating voltages of a memory device and other circuits.
The mismatch directly leads to a problem in that power consumption and access speed in memory writing cannot be improved even when the transistors are reduced in size.
The writing of “1” to the ferroelectric memory is performed by for example setting the bit line BL in FIG. 16 to a high with the word line WL in an on state and setting the plate line PL to a grounded state. Since the bit line BL is generally connected with many nonselected memory cells and thus has a very high load capacitance, charging and discharging of the bit line BL accounts for most of the power consumption in memory access.
For example, even when a logic within a chip can be operated at 1.0 V, 1.5 to 3 V needs to be applied to a bit line to effect polarization inversion of a cell capacitor. Thus power consumption required for charging and discharging the bit line is increased a number of times. In addition, since writing operation cannot be performed when the bit line is not completely charged to that potential, writing access time is lengthened.